DocumentCode :
2603335
Title :
Impact of flash annealing on performance and reliability of high-κ/metal-gate MOSFETs for sub-45 nm CMOS
Author :
Kalra, Pankaj ; Majhi, Prashant ; Heh, Dawei ; Bersuker, Gennadi ; Young, Chadwin ; Vora, Nikhil ; Harris, Rusty ; Kirsch, Paul ; Choi, Rino ; Chang, Man ; Lee, Joonmyoung ; Hwang, Hyunsang ; Tseng, Hsing-Huang ; Jammy, Rajarao ; Liu, Tsu-Jae King
Author_Institution :
Univ. of California, Berkeley
fYear :
2007
fDate :
10-12 Dec. 2007
Firstpage :
353
Lastpage :
356
Abstract :
The use of millisecond annealing to meet ultra-shallow junction (USJ) requirements for sub-45 nm CMOS technologies is imperative. In this study, a detailed investigation of the effects of flash annealing on MOSFETs with Hf-based gate dielectric and metal gate electrodes is presented. The flash anneal process is found to be compatible with the high-κ/metal gate stack, in terms of gate dielectric reliability, and effective to achieve the benefits of USJ. However, it can lead to significantly degraded MOSFET performance due to defect generation in the interfacial SiOx layer, unless a post-metallization anneal is performed.
Keywords :
CMOS integrated circuits; MOSFET; annealing; dielectric properties; Hf-based gate dielectric reliability; SiOx; USJ; flash annealing; high-κ-metal-gate MOSFET reliability; interfacial SiOx layer; metal gate electrodes; millisecond annealing; size 45 nm; sub45 nm CMOS technology; ultrashallow junction; CMOS process; CMOS technology; Electrodes; High K dielectric materials; High-K gate dielectrics; Implants; MOSFETs; Rapid thermal annealing; Temperature; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
Type :
conf
DOI :
10.1109/IEDM.2007.4418944
Filename :
4418944
Link To Document :
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