Title :
SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers
Author :
Cheng, Yung-Shou ; Lu, Hsin-Hung ; Chang, Michael ; Chang, Stephen ; Liu, Bob ; Wu, Ruey-Beei
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
With increasing demand on higher performance for high speed I/O links, the signal integrity-aware layout schemes and equalization have been attributed as the critical techniques to improve the eye diagram. This paper describes a synthetic design to enhance the system performance and its application to realistic high-speed blade servers. Simulation results are provided to validate the design concept, demonstrating significant improvement in eye height and width by 284% and 96.7%, respectively, for a SATA II link of 1.175 m length and 3 Gb/s data rate.
Keywords :
elemental semiconductors; high-speed integrated circuits; integrated circuit interconnections; integrated circuit layout; silicon; SATA II link; bit rate 3 Gbit/s; equalizer design; eye diagram; high speed I/O links; high-speed blade servers; signal integrity-aware layout schemes; size 1.175 m; Blades; Connectors; Equalizers; Impedance; Layout; Reflection; Servers; Anti-pad; blade servers; contact pads; eaulizer; intersymbol interference; through-hole via; via stub;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-9398-2
Electronic_ISBN :
pending
DOI :
10.1109/EPEPS.2011.6100226
