High Temperature Reverse Bias Testing at Wafer Level

The complex hybrids being developed today probably will be a critical reliability problem if a better method of screening semiconductors prior to assembly into the hybrid is not developed. This paper outlines an approach that is presently under development which appears to hold a great deal of promise. It allows for an all gold interconnect system, improves the yield by using burned in chips, and makes the semiconductor and interconnect system less dependent on good, hermetic packages. It appears that burning in and screening at wafer level is a cost effective method of improving the reliability of complex hybrids.