Title :
Passive model-order reduction of RLC circuits with embedded time-delay descriptor systems
Author :
Charest, Andrew ; Nakhla, Michel ; Achar, Ramachandra
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
Abstract :
In this paper, a new algorithm for passive model- order reduction of RLC networks with embedded general Time- Delay Descriptor (TDD) systems is presented. In addition, a new passivity verification algorithm for TDD systems is developed. Numerical results validating the proposed algorithms are also presented.
Keywords :
RLC circuits; delay circuits; embedded systems; signal processing; RLC circuit; TDD system; embedded time-delay descriptor system; passive model-order reduction; passivity verification algorithm; Algorithm design and analysis; Delay; Eigenvalues and eigenfunctions; Integrated circuit modeling; Linear matrix inequalities; Numerical models; RLC circuits;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2011 IEEE 20th Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-9398-2
Electronic_ISBN :
pending
DOI :
10.1109/EPEPS.2011.6100232
