A hardware sharing architecture for implementing the entire transforms in H.264/AVC video coding standard

H.264/AVC standard uses various transforms to improve the coding efficiency and quality. 4×4 Integer Discrete Cosine Transform (DCT) and Hadamard transforms are the transforms used in the early versions of H.264/AVC standard. The Fidelity Range Extension (FRExt) of this standard supports 8×8 integer DCT along with 4×4 integer DCT to achieve higher compression rate. In this paper we propose a hardware sharing pipelined architecture for realization of the entire forward and inverse integer DCT and also Hadamard transforms in H.264/AVC standard. The proposed architecture is synthesized using the synopsis synthesize tool and synthesize results indicate that this architecture is a resource efficient and fast implementation for the entire transforms in H.264/AVC encoder.