Title :
An efficient 175 MHz programmable FIR digital filter
Author :
Khoo, Kei-Yong ; Kwentus, Alan ; Willson, Alan N., Jr.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
Abstract :
An efficient 175-MHz programmable finite impulse response (FIR) digital filter is implemented. It uses a novel switchable unit-delay to allocate the optimal hardware resources to each filter tap. The authors´ prototype circuit can have up to 32 linear taps with 16-bit I/O in a die size of 5.9mm by 3.4mm using 1.2 μm CMOS technology. A simple recoding of the coefficient values results in a simplification of the digit multiplication hardware. On-chip testing circuitry permits the testing of the chip at a high frequency
Keywords :
CMOS digital integrated circuits; FIR filters; delay circuits; digital filters; multiplying circuits; programmable filters; 1.2 micron; 175 MHz; CMOS technology; coefficient values; die size; digit multiplication hardware; filter tap; linear taps; optimal hardware resources; programmable FIR digital filter; switchable unit-delay; CMOS technology; Clocks; Digital filters; Digital integrated circuits; Finite impulse response filter; Hardware; Laboratories; Latches; Resource management; Switching circuits;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.393660
