A High-performance Multi-level NAND Flash Memory with 43nm-node Floating-gate Technology

Author

Noguchi, M. ; Yaegashi, T. ; Koyama, H. ; Morikado, M. ; Ishibashi, Yutaka ; Ishibashi, Shojiro ; Ino, K. ; Sawamura, K. ; Aoi, T. ; Maruyama, Tetsuhiro ; Kajita, Akihiro ; Ito, Eisuke ; Kishida, Masako ; Kanda, K. ; Hosono, Keita ; Miyamoto, Sadaaki ; It

Author_Institution

Toshiba Corp., Yokohama

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

445

Lastpage

448

Abstract

Multi-level programming is demonstrated with 43 nm-node NAND floating-gate megabit cells for the first time, by thinning an inter-gate dielectric film to less than 13 nm. 43 nm-node cobalt-silicide control-gate and copper bit-line technologies are developed to achieve low resistances of the word lines and bit lines.

Keywords

NAND circuits; cobalt compounds; copper; dielectric thin films; flash memories; multivalued logic circuits; NAND floating-gate megabit cells; cobalt-silicide control-gate technology; copper bit-line technology; floating-gate technology; inter-gate dielectric film; multilevel NAND flash memory; multilevel programming; size 43 nm; Conductors; Copper; Dielectric films; Indium tin oxide; Memory management; Nonvolatile memory; Size control; Thickness control; Throughput; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4418969

Filename

4418969