Title :
An architecture for stereo image matching
Author :
Pissaloux, E.E. ; Coat, F. Le ; Bouayed, H.
Author_Institution :
Lab. de Robotique de Paris, CNRS, Fontenay-aux-Roses, France
Abstract :
This paper addresses a modified dynamic programming parallel algorithm, and its associated architecture of temporal and spatial complexity of O(N), with N number of processing elements involved in computation. The modification consists of the algorithm adaptation to image interest point matching and architecture optimization. The parallel algorithm simulates the designed architecture, validates it functionally, and allows temporal performance prediction. The proposed algorithm of low spatial and temporal complexities is very suitable for real time on board applications (autonomous robot guidance, trajectory matching, blind vision guidance...).
Keywords :
VLSI; computational complexity; digital signal processing chips; dynamic programming; image matching; image processing equipment; parallel algorithms; real-time systems; robot vision; stereo image processing; systolic arrays; VLSI architecture; algorithm adaptation; architecture optimization; image interest point matching; modified dynamic programming parallel algorithm; real time on board applications; spatial complexity; stereo image matching; systolic parallel asynchronous circuit; temporal complexity; temporal performance prediction; Algorithm design and analysis; Computational modeling; Computer architecture; Concurrent computing; Dynamic programming; Image matching; Parallel algorithms; Prediction algorithms; Predictive models; Robot vision systems;
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
DOI :
10.1109/APCCAS.2002.1115227