Author :
Nirschl, T. ; Philipp, J.B. ; Happ, T.D. ; Burr, G.W. ; Rajendran, B. ; Lee, M.H. ; Schrott, A. ; Yang, M. ; Breitwisch, T.M. ; Chen, C.F. ; Joseph, E. ; Lamorey, M. ; Cheek, R. ; Chen, S.-H. ; Zaidi, S. ; Raoux, S. ; Chen, Y.C. ; Zhu, Y. ; Bergmann, R. ;
Abstract :
We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4 bits/cell and a 32 kb memory page at 2 bits/cell are experimentally demonstrated.
Keywords :
semiconductor storage; 2-bit multilevel phase-change memory; 4-bit multilevel phase-change memory; highly optimized resistance distributions; multilevel write algorithm; word length 2 bit; word length 4 bit; Amorphous materials; CMOS technology; Crystallization; Electrodes; Etching; Lithography; Phase change materials; Phase change memory; Testing; Tin;
