Title :
Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches
Author :
Nikolos, D. ; Verges, H.T. ; Vazaios, A. ; Voulgaris, S.
Author_Institution :
Dept. of Comput. Eng. & Inf., Patras Univ., Greece
Abstract :
In this paper a yield model for single chip VLSI processors with two level on-chip caches is derived. Using this model and trace driven simulations the distribution of the faulty cache blocks into the first and second level caches can be determined so as to achieve a significant yield enhancement with the minimum performance degradation
Keywords :
VLSI; cache storage; integrated circuit modelling; integrated circuit yield; microprocessor chips; faulty two-level on-chip cache; performance degradation; simulation; single chip VLSI processor; yield model; Buildings; Cache memory; Computational modeling; Degradation; Electronic mail; Informatics; Manufacturing processes; Performance loss; Testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-7545-4
DOI :
10.1109/DFTVS.1996.571989
