Title :
Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS
Author_Institution :
Intel Corp., Hillsboro
Abstract :
This paper presents an overview of process variation effects, including examples of mitigation strategies and test methods. Experimental and theoretical comparisons are presented for 45 nm and 65 nm RDF. SRAM matching and interconnect variation is discussed for both 65 nm and 45 nm, including examples of process and design mitigation strategies. Use of ring oscillators for detailed measurement of within-wafer and within-die variation is illustrated for 65 nm and 45 nm products.
Keywords :
CMOS integrated circuits; SRAM chips; design for manufacture; integrated circuit interconnections; nanotechnology; SRAM matching; design for manufacturability; interconnect variation; nanoscale CMOS technology; process variation effects; random dopant fluctuation; ring oscillators; size 45 nm to 65 nm; CMOS logic circuits; CMOS process; CMOS technology; Logic design; Manufacturing processes; Process design; Random access memory; Resource description framework; Ring oscillators; Testing;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418976
