Title :
Implementing a complete test tool set in VHDL
Author :
Peymandoust, Armita ; Navabi, Zainalabedin
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented and a specific example for adaptive random test generation is explained in detail
Keywords :
circuit analysis computing; digital simulation; fault diagnosis; hardware description languages; logic CAD; logic testing; multiprocessing programs; programming environments; VHDL; adaptive random test generation; concurrent programming environment; digital system test algorithms; fault simulation; test tool set; uniform hardware netlist format; Analytical models; Application software; Concurrent computing; Digital systems; Engines; Hardware; Power system modeling; Programming environments; System testing; Timing;
Conference_Titel :
VHDL International Users' Forum, 1997. Proceedings
Conference_Location :
Arlington, VA
Print_ISBN :
0-8186-8180-2
DOI :
10.1109/VIUF.1997.623923
