DocumentCode :
2603940
Title :
A faster algorithm of minimizing AND-EXOR expressions
Author :
Hirayama, Takashi ; Nishitani, Yasuaki ; Sato, Toru
Author_Institution :
Dept. of Comput. & Inf. Sci., Iwate Univ., Japan
Volume :
2
fYear :
2002
fDate :
2002
Firstpage :
293
Abstract :
We propose a faster algorithm of minimizing AND-EXOR expressions. While it has been considered difficult to obtain the minimum AND-EXOR expression of a given function with six variables in a practical computing time, our algorithm can compute the minimum AND-EXOR expressions of any six-variable and some seven-variable functions practically. In this paper, we first present a naive algorithm that searches the space of expansions of a given n-variable function f for a minimum expression of f. The space of expansions are generated by using all combinations of (n-1)-variable product terms. Then, how to prune the branches in the search process and how to restrict the search space to obtain the minimum solutions are discussed as the key point of reduction of the computing time. Finally, a faster algorithm is constructed by using the methods discussed. Experimental results to demonstrate the effectiveness of these methods are also presented.
Keywords :
Boolean functions; logic CAD; logic gates; minimisation of switching nets; AND-EXOR expressions minimization; branch pruning; computing time reduction; fast algorithm; minimum solutions; n-variable function; search process; search space restriction; seven-variable functions; six-variable functions; space of expansions; Arithmetic; Circuit testing; Logic circuits; Logic functions; Minimization methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on
Print_ISBN :
0-7803-7690-0
Type :
conf
DOI :
10.1109/APCCAS.2002.1115235
Filename :
1115235
Link To Document :
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