Interconnect design for FPGAs under process variations for leakage power yield

Leakage power is a key challenge in VLSI design, and process variations have aggravated the problem. Interconnects have become very critical in modern VLSI designs and have started to play a major role in determining the power and performance of a design. Certain VLSI circuits such as FPGAs are interconnect dominated, such that their performance and power are largely governed by the interconnects on the chip. This work analyzes and proposes a variability-aware optimization technique for leakage power in interconnects of FPGAs, under delay constraints. Results indicate that up to 26% reduction in leakage variability can be obtained without any delay penalty.