A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT

The Discrete Wavelet Transform (DWT) is the basis for many image compression techniques, such as JPEG2000, MPEG-4, etc. The Spatial Combinative Lifting Algorithm (SCLA) based 2-D DWT/IDWT requires fewer computations than the conventional Lifting Based Implementation (LBI). In comparison with the LBI, SCLA with the 9/7 filter has 7/12 the number of multiplications. This paper proposes a novel VLSI architecture to compute multilevel SCLA based 2-D DWT/IDWT with the 9/7 filter. The line based transform is integrated with the SCLA scheme to reduce the hardware cost and achieve higher hardware utilization. Efficient organization of six line-buffer memories is used to address the high memory bandwidth requirements. This architecture can be used as a compact and efficient core for JPEG2000 VLSI implementation and various real-time image/video applications.