An area-efficient maximum/minimum detection circuit for digital and video signal processing

Author

Lee, Chen-Yi ; Juan, Shih-Chou ; Yang, Wen-Wei

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1993

fDate

3-6 May 1993

Firstpage

223

Abstract

A circuit for parallel bit-level maximum/minimum selection is presented. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from most significant bit (MSB) to least significant bit (LSB) and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns such as those required in digital and video signal processing

Keywords

application specific integrated circuits; digital signal processing chips; image coding; vector quantisation; video signal processing; area-efficient maximum/minimum detection circuit; data patterns; digital signal processing; label-updating scheme; least significant bit; most significant bit; parallel bit-level maximum/minimum selection; structure modularity; updating units; video signal processing; Circuit synthesis; Clocks; Equations; Phase detection; Timing; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.393698

Filename

393698