Title :
Practical dual-metal-gate dual-high-k CMOS integration technology for hp 32 nm LSTP utilizing process-friendly TiAlN metal gate
Author :
Kadoshima, M. ; Matsuki, T. ; Sato, M. ; Aminaka, T. ; Kurosawa, E. ; Ohta, A. ; Yoshinaga, H. ; Miyazaki, S. ; Shiraishi, K. ; Yamabe, K. ; Yamada, K. ; Aoyama, T. ; Nara, Y. ; Ohji, Y.
Author_Institution :
Semicond. Leading Edge Technol. Inc., Ibaraki
Abstract :
We propose a new dual-metal-gate dual-high-k CMOS integration technology using TaSiN gate HfSiON n-FET and TiAIN gate HfAlSiON p-FET for hp 32 nm low standby power (LSTP) CMOS devices. Low V, of p-FET, namely high effective work function of 4.8 eV was obtained due to spontaneous AIN-cap formation of TiAIN and subsequent intermixing between AIN-cap and HfSiON by high temperature annealing. There was no degradation in gate leakage current and electron mobility in TaSiN gate HfSiON n-FET even if TaSiN was formed after TiAIN removal. Thus, this technique is practical for realizing dual-metal-gate dual-high-k CMOS devices.
Keywords :
CMOS integrated circuits; electron mobility; field effect transistors; leakage currents; FET; LSTP; TiAIN metal gate; dual-metal-gate dual-high-k CMOS integration technology; electron mobility; gate leakage current; high temperature annealing; low standby power; Annealing; CMOS process; CMOS technology; Degradation; High K dielectric materials; High-K gate dielectrics; Lead compounds; Temperature; Tin; Wet etching;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4418992
