A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack

We show for the first time that conduction and valence band-edge effective work functions (WF) are achieved simultaneously by one single Dy₂O₃ capping layer on HfO₂ for both nMOS and pMOS with TaC_x-based metals. Low V_t´s (0.23 and -0.36 V) are obtained without degrading the EOT-J_G scalability and hole mobility. A model based on competing intermixes of cap/host dielectric and cap/metal is proposed to explain the positive WF shift with TaC_xN_y and the negative shift with TaC_x as compared to the uncapped HfO₂ reference. Finally, by developing a novel nitridation process to modify TaC_x into TaC_xN_y, this work shows that single-metal-single-dielectric gate stacks are feasible, allowing cost-effective low-V_t CMOS integration.