Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond

We demonstrate an amorphous higher-k (k>20) HfTiSiON gate dielectric for sub 32 nm node capable of low equivalent oxide thickness (EOT=0.84 nm). For the first time, we have addressed the thermodynamic instability of TiO₂ containing gate dielectrics achieving an acceptably thin SiO_x interface (0.7 nm) after 1070degC. 3-10times leakage current reduction is achieved with HfTiSiON vs. HfSiON due to a higher-k TiO₂ cap (k=40) on HfSiON. For the first time, an 8% I_on-I_off improvement of HfTiSiON vs. HfSiON is demonstrated. HfTiSiON shows I_on=1300 muA/mum at I_off=100 nA/mum for V_dd=1.2 V without stress engineering. HfTiSiON shows bias temperature instability (PBTI) and time dependent dielectric breakdown (TDDB) similar to HfSiON. This work is significant because it demonstrates higher-k scaling benefit and extension of high-k beyond Hf-oxides for sub-32 nm technologies.