Title :
Integration of DFM techniques and design automation
Author :
Waring, Thomas G. ; Allan, Gerard A. ; Walton, Anthony J.
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
Abstract :
This paper reports the integration of a yield enhancing router within the Alliance design automation environment. The system converts a high level description, using a subset of VHDL, to mask layout. The final layout has been made more robust to spot defects using a number of layout modification strategies within the routing network. The results indicate that these modifications significantly reduce the probability of faults for the device as a whole
Keywords :
circuit layout CAD; design for manufacture; high level synthesis; integrated circuit layout; integrated circuit yield; Alliance environment; DFM; VHDL subset; defects; design automation; fault probability; high level description; mask layout; routing network; yield; Circuit faults; Design automation; Design for manufacture; Fabrication; Integrated circuit technology; Poisson equations; Predictive models; Production; Robustness; Routing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-7545-4
DOI :
10.1109/DFTVS.1996.571991
