Rapid Circuit-based Optimization of Low Operational Power CMOS Devices

Author

Christie, P. ; Nackaerts, A. ; Hoffmann, T. ; Kumar, A.

Author_Institution

NXP-TSMC Res. Center, Leuven

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

573

Lastpage

576

Abstract

We demonstrate: (i) a silicon-calibrated, low computational complexity Verilog-A MOS model coupled to rapid library generation and characterization tool set within a commercial-grade design flow, (ii) the use of this design flow for the evaluation of TCAD-based transistors in high complexity circuits with iteration times of less than three hours, (iii) the design of 16-bit multiplier circuits with low operational (static + dynamic) power CMOS devices with power savings of 84% and 76% at 25degC and 60degC, respectively, compared to an unmodified 70 nm gate length CMOS process.

Keywords

CMOS integrated circuits; circuit optimisation; computational complexity; hardware description languages; integrated circuit design; multiplying circuits; power MOSFET; semiconductor device models; silicon; technology CAD (electronics); TCAD-based transistors; circuit-based optimization; commercial-grade design flow; computational complexity Verilog-A MOS model; low operational power CMOS device; multiplier circuits; rapid library generation; silicon-calibration; CMOS process; CMOS technology; Circuits; Computational modeling; Data mining; Hardware design languages; Libraries; MOS devices; Phased arrays; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4419003

Filename

4419003