DocumentCode :
2604467
Title :
A power efficient USB 2.0 device controller architecture and its implementation
Author :
Tiong Hong, T. ; Zeeshan, S. ; Abdullah, M.Z.
Author_Institution :
Intel Microelectron., Bayan Lepas, Malaysia
fYear :
2011
fDate :
14-17 June 2011
Firstpage :
388
Lastpage :
392
Abstract :
With the ubiquitous use of a USB 2.0 device controller in most of our electronic devices ranging from mobile handheld devices to external hard disks and gaming controllers, it is getting more and more important that a new power efficient USB 2.0 device controller architecture is define which addresses battery life issues in current devices. This paper will first describe how a USB 2.0 device controller works and the underlying root cause of its power inefficiency. The paper will then propose an architecture which is more power efficient using clock gating techniques as well as a fine grain power gating approach based on data traffic. The open source USB 2.0 device controller soft-core which is maintained by the OpenCores Organization will be used as a base design to be improved on.
Keywords :
computer architecture; control engineering computing; logic gates; peripheral interfaces; power aware computing; public domain software; ubiquitous computing; OpenCores organization; battery life; clock gating techniques; data traffic; electronic devices; external hard disks; gaming controllers; grain power gating approach; mobile handheld devices; open source USB 2.0 device controller soft-core; power efficient USB 2.0 device controller architecture; power inefficiency; ubiquitous use; Clocks; Computer architecture; Logic gates; Power dissipation; Protocols; Random access memory; Universal Serial Bus;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics (ISCE), 2011 IEEE 15th International Symposium on
Conference_Location :
Singapore
ISSN :
0747-668X
Print_ISBN :
978-1-61284-843-3
Type :
conf
DOI :
10.1109/ISCE.2011.5973855
Filename :
5973855
Link To Document :
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