• DocumentCode
    2604476
  • Title

    New In-Situ Process of Top Gate Nanocrystalline Silicon Thin Film Transistors Fabricated at 180 °C for the Suppression of Leakage Current

  • Author

    Park, Joong-Hyun ; Han, Sang-Myeon ; Choi, Young-Hwan ; Kim, Sun-Jae ; Han, Min-Koo

  • Author_Institution
    Seoul Nat. Univ., Seoul
  • fYear
    2007
  • fDate
    10-12 Dec. 2007
  • Firstpage
    595
  • Lastpage
    598
  • Abstract
    We have successfully fabricated top gate nanocrystalline silicon (nc-Si) thin film transistor (TFT) using an inductively coupled plasma chemical vapor deposition (ICP-CVD) at substrate temperature of 180°C with various nc-Si thicknesses. The field effect mobilities of conventional top gate TFTs with the nc-Si thicknesses of 60, 90 and 130 nm are 26, 77 and 119 cm2/Vsec due to the increase of nc-Si grain size, respectively. However, the leakage current measured at VGS=-4.4 V increased with increase of nc-Si thickness because channel resistance increased. We fabricated a new in-situ process in order to suppress leakage current. The new in-situ process for the protection of the interface from the native oxide and impurities in the air is the continuous deposition of nc-Si and SiO2 layers without any vacuum break. The leakage current of the nc-Si TFT was successfully suppressed from 5.2x10-9 to 3.6x10-10. A by employing the new in-situ process. The subthreshold swing was reduced from 274 to 230 mV/dec and the field effect mobility was improved from 77 to 99 cm2/Vsec, respectively.
  • Keywords
    atomic force microscopy; electron mobility; elemental semiconductors; hole mobility; leakage currents; nanoelectronics; nanostructured materials; plasma CVD; scanning electron microscopy; semiconductor thin films; silicon; surface morphology; thin film transistors; Si; atomic forced microscopy; conventional top gate TFT; field effect mobilities; in-situ process; inductively coupled plasma chemical vapor deposition; leakage current suppression; nanocrystalline silicon thin film transistor; nc-Si TFT fabrication; scanning electron microscopy; size 130 nm; size 60 nm; size 90 nm; substrate temperature; surface morphology; temperature 180 °C; Chemical vapor deposition; Current measurement; Electrical resistance measurement; Grain size; Leakage current; Plasma chemistry; Plasma temperature; Silicon; Substrates; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International
  • Conference_Location
    Washington, DC
  • Print_ISBN
    978-1-4244-1507-6
  • Electronic_ISBN
    978-1-4244-1508-3
  • Type

    conf

  • DOI
    10.1109/IEDM.2007.4419009
  • Filename
    4419009