A knowledge representation based parallel architecture for rule-based simulation applications

The authors propose a knowledge-representation-based parallel architecture for rule-based simulation applications. This architecture yields very high speedup and exploits inherent data parallelism that is present in the application. In addition, the proposed architecture also avoids the semantic gap that exists between an application and its implementation. Several hardware rule-based simulation applications with functionality were implemented on the Intel iPSC/2 hypercube. Two example applications with the experimental results are provided to demonstrate the approach