• DocumentCode
    2604503
  • Title

    A Failure Analysis Technique for Locating the Fail Site in MOSFET (LSI) Logic Chips with Sputtered SiO2 Passivation

  • Author

    Viele, Allan A.

  • Author_Institution
    International Business Machines Corporation, System Development Division, Manassas, Virginia 22110
  • fYear
    1974
  • fDate
    27120
  • Firstpage
    16
  • Lastpage
    21
  • Abstract
    This paper describes a technique used successfully to locate the fail site in MOSFET (LSI) Logic Chips. It is used to analyze modules or chips which fail functionally during electrical test. Signal tracing is employed to locate the fail site while dynamically exercising the chip. This technique emphasizes the analysis of AC fails (timing problems) and chips with sputtered SiO2 (Quartz) passivation.
  • Keywords
    Automatic testing; Circuit testing; Failure analysis; Large scale integration; Logic circuits; Logic devices; Logic testing; MOSFET circuits; Passivation; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1974. 12th Annual
  • Conference_Location
    Las Vegas, NV, USA
  • ISSN
    0735-0791
  • Type

    conf

  • DOI
    10.1109/IRPS.1974.362621
  • Filename
    4207999
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2604503