A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

Author

Nair, Rajesh ; Ryan, Gerry ; Farzaneh, Farivar

Author_Institution

Bay Networks Inc., Santa Clara, CA, USA

fYear

1997

fDate

19-22, Oct 1997

Firstpage

82

Lastpage

87

Abstract

Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates. The area and timing results of the hardware implementation are presented and compared with a conventional loop iteration technique (also described in this paper). The CRC-32 polynomial, commonly used for most computer network protocol standards, was chosen to implement the algorithm

Keywords

Boolean algebra; cyclic codes; data flow analysis; equations; error detection codes; hardware description languages; logic design; logic gates; polynomials; redundancy; timing; CRC circuit; CRC generator; CRC-32 polynomial; VHDL description; area; computer network protocol standards; cyclic redundancy check; data flow representation; hardware implementation; logic gates; logic synthesis; loop iteration technique; optimized Boolean equations; parameterizable data width; simulation-based algorithm; symbol based algorithm; timing; Circuit simulation; Circuit synthesis; Computer networks; Cyclic redundancy check; Equations; Hardware; Network synthesis; Polynomials; Protocols; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VHDL International Users' Forum, 1997. Proceedings

Conference_Location

Arlington, VA

Print_ISBN

0-8186-8180-2

Type

conf

DOI

10.1109/VIUF.1997.623934

Filename

623934