Title :
Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications
Author :
Hudait, M.K. ; Dewey, G. ; Datta, S. ; Fastenau, J.M. ; Kavalieros, J. ; Liu, W.K. ; Lubyshev, D. ; Pillarisetty, R. ; Rachmady, W. ; Radosavljevic, M. ; Rakshit, T. ; Chau, Robert
Author_Institution :
Intel Corp., Hillsboro
Abstract :
This paper describes for the first time, the heterogeneous integration of In0.7Ga0.3As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In0.7Ga0.3As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.
Keywords :
III-V semiconductors; indium compounds; quantum well devices; silicon; In0.7Ga0.3As; composite buffer architecture; enhancement mode; heterogeneous integration; high speed; logic applications; low voltage; quantum well device; quantum well transistor; voltage 0.5 V; Buffer layers; CMOS logic circuits; Degradation; Electron mobility; Gallium arsenide; Indium gallium arsenide; Logic devices; Low voltage; Silicon; Temperature;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4419017
