An analog CMOS rank-order extractor with O(N) complexity using maximum/winner-take-all circuit

Author

Hung, Y.-C. ; Liu, B.D.

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

2

fYear

2002

fDate

2002

Firstpage

389

Abstract

Design of a new analog rank-order extractor with input expandable capability is described. An extraction for rth rank order is defined by identifying the rth largest magnitude of input variables, which is useful for fuzzy controllers and artificial neural networks. The proposed two-side search for rank-order finding greatly improves the response time. An experimental chip was fabricated using a 0.5-μm CMOS technology. The results of HSPICE post-layout simulation show that the response time of this circuit is approximately 700 ns for each rank-order operation, that the input dynamic range is about 5 μA to 30 μA, and that the resolution is 1 μA for 3.3 V supply voltage.

Keywords

CMOS analogue integrated circuits; SPICE; analogue processing circuits; circuit complexity; circuit simulation; integrated circuit measurement; integrated circuit modelling; 0.5 micron; 3.3 V; 5 to 30 muA; 700 ns; analog CMOS rank-order extractor; artificial neural networks; complexity; fuzzy controller; input dynamic range; input expandable capability; input variables magnitude; maximum/winner-take-all circuit; measurement resolution; rank-order operation; response time; signal-processing circuits; supply voltage; two-side search; Artificial neural networks; CMOS analog integrated circuits; CMOS technology; Circuit simulation; Delay; Dynamic range; Fuzzy control; Fuzzy neural networks; Input variables; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on

Print_ISBN

0-7803-7690-0

Type

conf

DOI

10.1109/APCCAS.2002.1115273

Filename

1115273