Title :
Logic Performance of 40 nm InAs HEMTs
Author :
Kim, Dae-Hyun ; del Alamo, Jesús A.
Author_Institution :
Massachusetts Inst. of Technol. (MIT), Cambridge
Abstract :
We have experimentally evaluated the logic performance of 40 nm InAs HEMTs. For a barrier thickness of 4 nm, we find that 40 nm InAs HEMTs exhibit excellent logic figures of merit and scalability at VDS = 0.5 V, such as DIBL = 80 mV/V, S = 70 mV/dec, and fT = 475 GHz. These remarkable results arise from the combination of the outstanding transport properties of InAs channel, and the use of a thin insulator and a thin channel. In addition, these devices exhibit ION/IOFF ratios in excess of 104, revealing that band-to-band tunneling is not a significant concern in our device design. Our InAs HEMTs exhibit an injection velocity at the virtual source point that is a factor of 1.6X higher than state-of-the-art Si n-MOSFETs, in spite of the significantly lower supply voltage.
Keywords :
III-V semiconductors; high electron mobility transistors; indium compounds; tunnelling; HEMT logic performance; InAs; size 40 nm; thin insulator; transport properties; Etching; HEMTs; Indium phosphide; Insulation; Logic devices; MODFETs; Process control; Scalability; Tin; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4419018