A new high-performance CMOS GHz power amplifier design with common-mode signal cancellation technique

Author

Wu, Chng-Yu ; Wen-Chieh Wang ; Chen, Tzung-Ming

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan

Volume

2

fYear

2002

fDate

2002

Firstpage

395

Abstract

This work describes a novel common-mode signal rejection method for power amplifiers. A power amplifier with standard 1P5M 0.25 μm CMOS technology was simulated and analyzed. This common-mode signal cancellation method makes the performance, in terms of output power and efficiency of the power amplifier, more immune to input common-mode signals than conventional power amplifiers. Simulated results indicate that this fully balanced differential power amplifier yields 24 dBm output power at 2.45 GHz, from a 3.3 V power supply. The simulated drain efficiency is 33.21%, and the overall power-added efficiency is 32.84%. The power amplifier is highly linear.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF power amplifiers; circuit simulation; differential amplifiers; integrated circuit design; integrated circuit modelling; power integrated circuits; 0.25 micron; 2.45 GHz; 3.3 V; 32.84 percent; 33.21 percent; CMOS GHz power amplifier design; balanced differential power amplifier; common-mode signal cancellation technique; common-mode signal rejection method; highly linear power amplifier; input common-mode signal immunity; output power; power supply; power-added efficiency; simulated drain efficiency; standard 1P5M CMOS technology; Circuits; Degradation; Frequency; High power amplifiers; Power amplifiers; Power generation; Power harmonic filters; Radiofrequency amplifiers; Signal design; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on

Print_ISBN

0-7803-7690-0

Type

conf

DOI

10.1109/APCCAS.2002.1115275

Filename

1115275