Title :
Technology Circuit Co-Design for High Performance Logic
Author :
Bernstein, Kerry ; Rohrer, Norman J.
Author_Institution :
IBM TJ Watson Res. Center, Yorktown Heights
Abstract :
Achieving maximum logic performance at minimum power consumption in deeply scaled CMOS technologies requires the cooperative design of technology, circuits, and architecture. The objective of this paper is to examine the interaction of technology and circuits in highly synchronous logic, and the factors which influence the size of the functionality window and the circuit-limited-yield across process and over time. Specific circuit topology as well as generic chip responses will be explored and tied back to underlying idiosyncrasies of the field effect transistor.
Keywords :
CMOS logic circuits; MOSFET; integrated circuit design; integrated circuit yield; logic design; network topology; chip responses; circuit topology; circuit-limited-yield; deeply scaled CMOS technologies; field effect transistor; functionality window; high performance logic; highly synchronous logic; technology circuit co-design; CMOS logic circuits; CMOS technology; Circuit topology; Delay; Energy consumption; Logic circuits; Logic design; Logic devices; Microprocessors; Robustness;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4419022
