Title :
An Adaptive Design of SRAM Memory Cell
Author :
Ishibashi, Koichiro
Author_Institution :
Renesas Technol. Corp., Tokyo
Abstract :
SRAM arrays play vital roles as on-chip memories in SOCs. As the dimension of MOS transistors is reduced, variability of MOS transistors becomes large, so that the electrical stability of SRAM memory cell has been deteriorated. Also, gate tunneling leakage and GIDL (Gate Induced Drain Leakage) have become dominant power of the SRAM array.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; leakage currents; system-on-chip; MOS transistors; SRAM arrays; SRAM memory cell design; electrical stability; gate induced drain leakage; gate tunneling leakage; system-on-chip memories; Adaptive arrays; CMOS technology; Circuit stability; Dynamic voltage scaling; MOSFETs; Manufacturing; Random access memory; Sensitivity analysis; Timing; Tunneling;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4419025
