Redesign of a generic VHDL model template for SRAMs

To reduce the time spent in writing and testing SRAM models, a method to automatically construct and deliver efficient SRAM models to the modeling community was developed. A new template, based on older existing models, targeted improvements in parameterization of variables and modularization of functionality, as well as efficient use of VHDL. The new template was posted to the World Wide Web and provides a fast and easy way for modelers to generate a wide range of SRAM models