A comprehensive approach to assessing and analyzing 1149.1 test logic

In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 standard while providing a precise list of errors as well as good debug and diagnostic information using graphical analysis. The paper provides a review of the methods used to perform the logic verification. We introduce an efficient technique for verifying the correspondence of chip I/O with the boundary scan register and for verifying large scan registers. The tool is independent of how the test logic is instantiated. The tool requires only the design netlist, cell library definition, and its BSDL identifying what 1149.1 test logic has been implemented. A result on current large ASIC designs is included based on Gillis et al. (1996).