Title :
VHDL models supporting a system-level design process: a RASSP approach
Author :
Debardelaben, James A. ; Madisetti, Vijay K. ; Gadient, Anthony J.
Author_Institution :
Center for Signal & Image Process., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4× improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost
Keywords :
application specific integrated circuits; circuit analysis computing; costing; digital signal processing chips; digital simulation; hardware description languages; high level synthesis; military computing; software engineering; software prototyping; synthetic aperture radar; DARPA; RASSP program; Rapid Prototyping of Application-Specific Signal Processors; Tri-Services; US Department of Defense; VHDL models; cosimulation; cost; coverification; cycle time; logic design; manufacturing; parametric cost modeling; synthetic aperture radar system; system-level design process; time; virtual prototyping process; Costs; Digital signal processing; Hardware; Process design; Prototypes; Signal design; Signal processing; System-level design; Time to market; Virtual prototyping;
Conference_Titel :
VHDL International Users' Forum, 1997. Proceedings
Conference_Location :
Arlington, VA
Print_ISBN :
0-8186-8180-2
DOI :
10.1109/VIUF.1997.623949