DocumentCode :
2605002
Title :
Hardware/software codesign of a scalable embedded radar signal processor
Author :
Buenzli, Charles ; Owen, Lee ; Rose, Fred
Author_Institution :
Omniview Design Inc., Pittsburgh, PA, USA
fYear :
1997
fDate :
19-22, Oct 1997
Firstpage :
200
Lastpage :
208
Abstract :
The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using CosmosTM, simulated with QuickHDLTM , and analyzed with Cosmos. Results for a Mercury RACEwayTM architecture are presented
Keywords :
circuit analysis computing; digital signal processing chips; digital simulation; hardware description languages; high level synthesis; radar signal processing; real-time systems; software engineering; COTS DSP boards; Cosmos; Mercury RACEway; QuickHDL; RASSP; VHDL performance models; hardware architectures; hardware software codesign; performance modeling methodology; scalable embedded radar signal processor; simulation; software architectures; Computer architecture; Digital signal processing; Doppler radar; Embedded software; Hardware; Partitioning algorithms; Pulse compression methods; Radar signal processing; Signal processing; Software architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VHDL International Users' Forum, 1997. Proceedings
Conference_Location :
Arlington, VA
Print_ISBN :
0-8186-8180-2
Type :
conf
DOI :
10.1109/VIUF.1997.623951
Filename :
623951
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2605002
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