DocumentCode
2605058
Title
A model-year architecture approach to hardware reuse in digital signal processor system design
Author
Wedgwood, Janet ; Buchanan, Greg
Author_Institution
Lockheed Martin Adv. Technol. Labs., Camden, NJ, USA
fYear
1997
fDate
19-22, Oct 1997
Firstpage
231
Lastpage
240
Abstract
This paper describes our team´s hardware model-year architecture (MYA) approach to develop cost-effective signal processors that can be applied to a wide range of military and commercial applications. We present an overview of the MYA approach and describe the framework. We introduce two key hardware architectural interfaces: the Standard Virtual Interface (SVI) and the Reconfigurable Network Interface (RNI). Next we describe several implementations of the SVI and RNI to illustrate how they would be used and some of the issues involved in implementing this approach. We discuss how the MYA relates to other efforts in the area of standard interfaces such as PCI (Peripheral Component Interconnect), PacketWay, the Virtual Microarchitecture Interface (VMI) and the Virtual Socket Interface Alliance (VSIA). Finally, we present our conclusions
Keywords
computer architecture; computer interfaces; reconfigurable architectures; signal processing; digital signal processor; hardware reuse; model-year architecture; signal processors; Computer architecture; Digital signal processors; HDTV; Hardware; Process design; Signal design; Signal processing; Software libraries; Software prototyping; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
VHDL International Users' Forum, 1997. Proceedings
Conference_Location
Arlington, VA
Print_ISBN
0-8186-8180-2
Type
conf
DOI
10.1109/VIUF.1997.623955
Filename
623955
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