On comparing different modeling styles [VHDL]

VHDL plays a dominating role in today´s system designs. Its primary application domain is currently focussed on RTL descriptions. One approach in dealing with the still dramatically increasing complexity of digital systems is to use VHDL more and more for executable specifications and complex test-benches. In this paper, we present the comparison results of models describing the same design unit using a set of different modeling styles in the domains of value representation, time representation and description style. We did not exclusively use VHDL, but took Ada programs into consideration describing the same unit using the same level of abstraction