Architecture of neural synaptic array, design and simulation

Author

He, Michel ; Klein, Jacques-Olivier ; Belhaire, Eric

Author_Institution

IEF, CNRS, Orsay

fYear

2007

fDate

2-5 Aug. 2007

Firstpage

601

Lastpage

604

Abstract

In this paper, we present the design of artificial neural network architecture to implement the look-up table of reconfigurable circuits. The various cells of schematic used only the carbon nanotubes semiconductors (CNTFET), and the non volatile multi-level resistance. The compatibility between CNTFET and non volatile multi-level resistance in the state of the art has been studied. Then the electrical circuit simulation results demonstrate successful learning of the linearly separable logical functions.

Keywords

carbon nanotubes; electrical resistivity; field effect transistors; neural net architecture; semiconductor devices; C; artificial neural network architecture; carbon nanotubes semiconductors; electrical circuit simulation; field effect transistor; neural synaptic array; nonvolatile multilevel resistance; Carbon nanotubes; Circuits; Computational modeling; Computer architecture; Electric resistance; Immune system; Nanoscale devices; Rails; Read-write memory; Table lookup; Associative processing architecture; Multi-level memories; Nanoscale programmable devices; Neural synaptic array;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology, 2007. IEEE-NANO 2007. 7th IEEE Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-0607-4

Electronic_ISBN

978-1-4244-0608-1

Type

conf

DOI

10.1109/NANO.2007.4601263

Filename

4601263