Fault tolerant structures for nanoscale gates

Predicted device reliability for nanoelectronics indicates that redundant design will be necessary to build reliable nanosystems. Up to date, several fault tolerant techniques have been proposed and analyzed. However, the fabrication complexity of those circuits, which directly affects the final circuit reliability, is not usually considered. In this paper, we compare two fault tolerant techniques, NAND Multiplexing (NM) and Averaging Cells (AC), as possible solutions to improve the nanoscale gate reliability. First, we propose nanodevice specific layouts for the two techniques. Then, we introduce nanotechnology oriented models to evaluate the area cost and reliability of the gates. Our simulations indicate that NM based gates are more reliable than AC gates when the error probabilities of the circuit parts are lower than 0.003. However, when this value is exceeded (which is expected for electronic nanotechnologies) AC gates are more reliable at a lower area cost.