New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise

Author

Tian, Yu ; Huang, Ru ; Wang, Yiqun ; Zhuge, Jing ; Wang, Runsheng ; Liu, Jia ; Zhang, Xing ; Wang, Yangyuan

Author_Institution

Peking Univ., Beijing

fYear

2007

fDate

10-12 Dec. 2007

Firstpage

895

Lastpage

898

Abstract

A new method to fabricate self-aligned silicon nanowire transistors (SNWTs) has been realized on bulk silicon substrate by fully epi-free compatible CMOS technology. The SNWTs exhibit excellent immunity of short-channel effects (SCEs) and achieve high I_on/I_off ratio of 2.6times10⁸. The transportation characteristics, ballistic efficiency and low frequency noise of SNWTs are investigated for the first time.

Keywords

1/f noise; MOSFET; nanowires; semiconductor device noise; silicon; ballistic efficiency; bulk silicon substrate; carrier transport; epi-free compatible CMOS technology; low frequency noise; self-aligned silicon nanowire transistors; short-channel effects; transportation characteristics; CMOS process; CMOS technology; Etching; Fabrication; Low-frequency noise; MOSFETs; Resistance heating; Silicon; Substrates; Transportation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2007. IEDM 2007. IEEE International

Conference_Location

Washington, DC

Print_ISBN

978-1-4244-1507-6

Electronic_ISBN

978-1-4244-1508-3

Type

conf

DOI

10.1109/IEDM.2007.4419094

Filename

4419094