A Study of Surface Charge Induced Inversion Failure of Junction Isolated Monolithic Silicon Integrated Circuits

The development of charge on the dielectric surface of junction isolated monolithic SICs can result in significant reductions in operating life. The transient and steady state characteristics of IC failure caused by the development of charge on the dielectric surface have been studied under room ambient conditions by monitoring the current through the inversion layer formed between circuit components of like conductivity type. The results of this study indicate that this IC failure mechanism is sensitive to IC layout geometry and suggest that conservative junction isolated monolithic SIC designs should have an inversion threshold voltage greater than the operating voltage.