Title :
Highly Scalable Vertical Double Gate NOR Flash Memory
Author :
Cho, Hoon ; Kapur, Pwan ; Kalavade, Pranav ; Saraswat, Krishna C.
Author_Institution :
Stanford Univ., Stanford
Abstract :
A Sub-50 nm body thickness (TSi), vertical channel (not FINFET), double gate, multi-bit NOR flash cell is fabricated on bulk-silicon substrate and is electrically characterized. This floating gate, conventional flash cell (no exotic materials), is potentially scalable with below 8F2 size beyond 32 nm node and is enabled by several key unit process innovations. The device is extensively characterized for program/erase, endurance, and charge interference on a shared thin body, which is important for scalability, density and multi-bit operation.
Keywords :
NOR circuits; flash memories; bulk-silicon substrate; conventional flash cell; double gate NOR flash memory; floating gate; Computational Intelligence Society; Etching; FinFETs; Flash memory; Interference; Nonvolatile memory; Oxidation; Protection; Scalability; Technological innovation;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4419101
