A flexible architecture for H.263 video coding

Author

Garrido, Matias J. ; Sanz, César ; Jiménez, Marcos ; Meneses, Juan M.

Author_Institution

Univ. Politecnica de Madrid, Spain

fYear

2002

fDate

2002

Firstpage

70

Lastpage

77

Abstract

In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.

Keywords

computer architecture; discrete cosine transforms; field programmable gate arrays; motion estimation; reduced instruction set computing; video coding; DCT; FPGA; H.263 video coding; IDCT; RISC processor; Rec. H.263; bit-stream generation; external video memory; flexible architecture; input video signal; motion compensation; motion estimation; preprocessing modules; quantizers; specialized processors; standard video sequences; synthesizable Verilog; video coder; Cameras; Data preprocessing; Discrete cosine transforms; Motion compensation; Motion control; Motion estimation; Process control; Processor scheduling; Reduced instruction set computing; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design, 2002. Proceedings. Euromicro Symposium on

Print_ISBN

0-7695-1790-0

Type

conf

DOI

10.1109/DSD.2002.1115353

Filename

1115353