DocumentCode
2606158
Title
New Generation of Z-RAM
Author
Okhonin, S. ; Nagoga, M. ; Carman, E. ; Beffa, R. ; Faraoni, E.
Author_Institution
PSE-B, Lausanne
fYear
2007
fDate
10-12 Dec. 2007
Firstpage
925
Lastpage
928
Abstract
A new generation of the single transistor floating body DRAM is introduced for the first time. The new memory is largely based on the bipolar transistor existing in the MOS structure. The memory´s main features are high margin, low-power consumption, and scalability.
Keywords
DRAM chips; MOS memory circuits; bipolar transistors; MOS structure; Z-RAM; bipolar transistor; device scalability; single transistor floating body DRAM; Bipolar transistors; Ionization; Logic; MOS capacitors; MOSFETs; Random access memory; Read-write memory; Scalability; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location
Washington, DC
Print_ISBN
978-1-4244-1507-6
Electronic_ISBN
978-1-4244-1508-3
Type
conf
DOI
10.1109/IEDM.2007.4419103
Filename
4419103
Link To Document