DocumentCode :
2606172
Title :
Configurable memory organisation for communication applications
Author :
Soininen, Juha-Pekka ; Pelkonen, Antti ; Roivainen, Jussi
Author_Institution :
VTT Electron. (Tech. Res. Centre of Finland), Oulu, Finland
fYear :
2002
fDate :
2002
Firstpage :
86
Lastpage :
93
Abstract :
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done by controlling the DSP processor´s access to memory buses with an external processor and switches. The configurable memory organisation allows the scaling of system capacity to the needs of the applications and makes the use of the capacity more effective. The architecture was modelled and evaluated using a systemC simulator and workload models. The clock frequency can be reduced by up to 25% if a configurable memory system is used instead of a bus-based shared memory. The memory latency with configurable memory organisation was less than 50% of the latency of the shared memory solution.
Keywords :
digital signal processing chips; memory architecture; transceivers; video coding; DSP processor memory buses; Hiperlan/2 transceiver baseband processing; MPEG2 decoding; SystemC simulator; bus-based shared memory; clock frequency; communication applications; configurable memory organisation; memory latency; memory system; system capacity; workload models; Baseband; Communication switching; Communication system control; Control systems; Decoding; Delay; Digital signal processing; Process control; Switches; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design, 2002. Proceedings. Euromicro Symposium on
Print_ISBN :
0-7695-1790-0
Type :
conf
DOI :
10.1109/DSD.2002.1115355
Filename :
1115355
Link To Document :
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