Title :
Extremely Low-voltage and High-speed Operation Bulk Thyristor-SRAM/DRAM (BT-RAM) Cell with Triple Selective Epitaxy Layers (TEL)
Author :
Sugizaki, T. ; Nakamura, M. ; Yanagita, M. ; Shinohara, M. ; Ikuta, T. ; Ohchi, T. ; Kugimiya, K. ; Kanda, S. ; Yagami, K. ; Oda, T.
Author_Institution :
Sony Corp., anagawa
Abstract :
We have successfully developed an alternative SRAM cell for the first time using a bulk thyristor-RAM (BT-RAM) with triple selective epitaxy layers (TEL) for anode, n-base, and cathode. The n-base of the pnp transistor is a key for the thyristor characteristics. We optimized both the thickness and the dopant concentration of the n-base by using an in-situ doped selective epitaxy technique. We obtained high current gain (beta values) for the pnp transistor in a thyristor, and the TEL BT-RAM cell was thus able to read/write at 200 ps at 0.6 V. It also showed good retention characteristics even at 125degC and the possibility of good scalability for a gate length of 45 nm and beyond. The TEL BT-RAM cell is therefore a promising alternative SRAM and DRAM cell for the future generations.
Keywords :
DRAM chips; SRAM chips; epitaxial layers; semiconductor doping; thyristors; transistor circuits; bulk thyristor-DRAM; bulk thyristor-SRAM; dopant concentration; pnp transistor; size 45 nm; temperature 125 C; triple selective epitaxy layers; voltage 0.6 V; Anodes; Cathodes; Costs; Energy consumption; Epitaxial growth; Random access memory; Scalability; Thickness control; Thyristors; Voltage;
Conference_Titel :
Electron Devices Meeting, 2007. IEDM 2007. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-1507-6
Electronic_ISBN :
978-1-4244-1508-3
DOI :
10.1109/IEDM.2007.4419105