Overview of power/ground effects on data eye and clock jitter: from board resonance to silicon substrate coupling

In high speed digital systems, clean clock signal and data signal are guaranteed by a clean power supply network. This paper shows how power supply network affects clock jitter and data eye pattern at each power hierarchy level, that is, board level, package level, on-chip level and silicon substrate coupling level. In particular, this paper shows the most dominant factors affecting data eye and clock jitter by observing relations of each power level coincidentally.