Title :
Lead-free plating for semiconductor devices qualification & implementation
Author :
Sriyarunya, Anocha ; Schetty, Rob
Author_Institution :
FASL (Thailand) Ltd., Nonthaburi, Thailand
Abstract :
This paper presents the findings of a series of experiments to evaluate various commercial lead-free plating alternatives, including tin, tin-copper and tin-bismuth products. Three different IC package types (TSOP 48, PLCC 32 and SOIC44) were used in both off line and in a production environment to evaluate solderability aspects including plating thickness, ionic impurity, morphology grade, solder whisker growth, solderability (tests under steam-age and bake conditions) and lead pull tests of mounted packages. Since no lead-free plating standards of quality were available at the time of the study, normal solder plating standards were used as a reference. Initial experiments revealed solderability issues (especially poor morphology grades and whiskering with both tin-bismuth and tin-copper materials). Tin plating looked the most promising material. Tin and tin-bismuth plating were further investigated in production processes to attempt to eliminate the initial quality issues, and to develop, fine-tune and optimize the plating process. The extensive experiments of this study of lead-free plating has yielded a great amount of information pertaining to the different chemistries of the different plating types, has identified a number of production concerns, and suggests process parameters for tin and tin-bismuth plating types that makes these materials viable replacements for tin-lead plating.
Keywords :
bismuth alloys; copper alloys; crystal morphology; integrated circuit packaging; integrated circuit testing; quality control; solders; tin; tin alloys; whiskers (crystal); IC packaging; Sn; SnBi; SnCu; bake conditions; ionic impurity; lead-free solder plating quality standards; morphology grade; mounted package lead pull tests; plating thickness; semiconductor device lead-free plating; solder whisker growth; solderability; steam-age conditions; Environmentally friendly manufacturing techniques; Integrated circuit packaging; Integrated circuit testing; Lead compounds; Morphology; Production; Qualifications; Semiconductor device packaging; Semiconductor devices; Tin;
Conference_Titel :
Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
Print_ISBN :
0-7803-8205-6
DOI :
10.1109/EPTC.2003.1271491