DocumentCode
2606820
Title
Layout-driven detection of bridge faults in interconnects
Author
Liu, Tong ; Chen, Xiaotao ; Lombardi, Fabrizio ; Salinas, J.
Author_Institution
Actel Corp., Sunnyvale, CA, USA
fYear
1996
fDate
6-8 Nov 1996
Firstpage
105
Lastpage
113
Abstract
This paper presents a new approach to fault detection of interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults by a novel weighted graph approach. This graph is then analyzed to appropriately schedule the order of test compaction and execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weights of the new adjacency graph as figure of merit. The advantage of the proposed approach is that on average, early detection of faults is possible using a number of tests significantly smaller than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still requiring a small number of vectors
Keywords
automatic testing; circuit analysis computing; fault diagnosis; integrated circuit interconnections; integrated circuit layout; integrated circuit testing; scheduling; bridge faults; critical area extraction; edge weights; fault detection; interconnect faults; layout physical characteristics; layout-driven detection; node weights; realistic fault model; scheduling; structural methodology; test compaction; test generation; weighted graph approach; Bridge circuits; Character generation; Circuit faults; Circuit testing; Computer science; Data mining; Fault detection; Field programmable gate arrays; Integrated circuit interconnections; Processor scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location
Boston, MA
ISSN
1550-5774
Print_ISBN
0-8186-7545-4
Type
conf
DOI
10.1109/DFTVS.1996.572005
Filename
572005
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